This invention relates to semiconductor memory devices and a method of manufacture, and more particularly of a onetransistor dynamic read/write memory cell array.
Dynamic read/write memory cells made by the doublelevel polysilicon N-channel self-alligned process commonly used in the industry are shown in U.S. Pat. No. 4,240,092, by C-K Kuo, assigned to Texas Instruments, as well as in Electronics, Feb. 19, 1976, pp. 116-121, May 13, 1976, pp. 81-86, and Sept. 28, 1978, pp. 109-116.
Although the double-level polysilicon process has proved to be quite successful and many hundreds of millions of memory devices have been made in this way, there is nevertheless added cost and degradation in yield due to the additional process steps compared to a single level process. Further, the classic cell layout uses a transistor which has a channel length determined by the amount of overlap of the two poly levels, making the characteristics of the transistor difficult to control. Single level polysilicon dynamic RAM cells as seen in U.S. Pat. No. 4,055,444, issued to G. R. Mohan Rao, assigned to Texas Instruments, ordinarily use a continuous polysilicon strip as the capacitor bias line. When attempting to lay out this type of single level poly cell in small cell size with the bit lines close together, problems arise in routing the capacitor bias lines, and the fact that a metal-to-poly contact is needed for each transistor is undesirable.
It is the principal object of this invention to provide an improved dynamic read/write memory cells. Another object is to provide a dynamic memory of more expedient layout and small cell size. An additional object is to provide a dense array of dynamic memory cells, made by a more efficient method. A further object is to provide an improved way of making dynamic memory cells without using double-level polysilicon in the array. Another object is to avoid relying upon features such as polysilicon lines for capacitor bias, and alignment precision in defining transistor channel lengths in dynamic memory cells, and to reduce cost by sharing a contact between two memory cells, thus reduced complexity in wafer fabrication.